Fast Fiber-to-Chip Peak Search for Wafer- Level Testing of Photonic Integrated Circuits

Optical input/output testing is the throughput bottleneck of wafer-level photonic integrated circuit (PIC) manufacturing: every device under test first requires active sub-micrometer alignment of an optical probe before any measurement can begin. This application note describes a production wafer-test system in which two TRITOR 100 SG three-axis piezo nanopositioning stages, each driven by an NV 40/3 CLE three-channel controller, perform the fast fiber-to-chip peak search on the input and output side of the device under test. An externally generated spiral trajectory is applied through the analog modulation input of the controller, while the strain-gauge position monitor output is sampled synchronously with the photodiode power signal. The result is a position-referenced coupling map acquired in a single open-loop scan of approximately 0.8 s, contributing to a total per-site alignment time of approximately 5 s – compatible with passive-device test cycles of around 10 s and full-wafer optical test runs measured in hours rather than days.

Data center interconnects are migrating from electrical to optical signaling. Silicon photonics and co-packaged optics (CPO) move the optical interface from the faceplate of the switch directly to the package of the ASIC, promising higher bandwidth density and lower energy per bit for AI and hyperscale workloads. Market analysts consistently project annual growth rates of 25–30% for silicon photonics and co-packaged optics over the next decade, driven primarily by AI data center infrastructure.

This transition has a manufacturing consequence that is easy to underestimate: photonic chips must be tested optically, at wafer level, before dicing and packaging. Unlike electronic die, a photonic die cannot be qualified through electrical probing alone– light must be coupled into and out of on-chip waveguides for every device under test. Because co-packaged assemblies have very limited rework ability, known-good-die assurance at wafer level is not optional; a single untested bad die can scrap an entire multi-die package.

The industry consensus is equally clear about where the cost sits: optical alignment is the dominant time and cost driver in photonic test and packaging, with packaging and alignment commonly cited as up to 80% of total photonic module cost. Every photonic wafer prober, every test house and every PIC manufacturer therefore faces the same core problem – how to find the optical coupling maximum between a fiber probe and an on-chip coupler in seconds, thousands of times per wafer, around the clock.

A single-mode fiber has a field diameter of roughly 10 μm; onchip edge couplers and grating couplers exhibit 1-dB alignment tolerances on the order of ±0.5 to ±1 μm, and significantly tighter for high-efficiency spot-size converters. No machine-vision or mechanical reference can place a probe within these tolerances repeatably. The only valid reference is the optical power itself – alignment must be performed actively, by scanning the probe and maximizing the measured coupling.

The arithmetic is unforgiving. A wafer-level optical-optical (OO) test of a fully populated wafer can occupy a prober for six to seven hours even when each passive device is tested in approximately ten seconds. Within that ten-second budget, the optical alignment – typically performed independently on the input and the output side of the device – must not consume more than a few seconds, including coarse capture and fine peak search on both probes. Every additional second of alignment time per site adds roughly an hour of prober time per wafer at 3,000+ test sites.

Piezo actuators are the only actuator class fast and fine enough for this task, but they confront the system designer with a dilemma:

Most commercial “alignment engine” products resolve this dilemma inside a closed, proprietary controller. That is a valid approach – but it forces the equipment builder to adopt the vendor’s controller ecosystem, algorithms and software stack, and it makes the alignment module a black box inside the tool.

A manufacturer of photonic wafer-test equipment integrated PSJ piezo systems into an automated prober for optical-optical and optical-electrical chip testing. The architecture separates coarse and fine positioning cleanly:

The decisive architectural element is the synchronous acquisition of the Monitor signal. The strain-gauge sensors integrated in the TRITOR 100 SG measure the actual motion of the stage platform; the NV 40/3 CLE makes this measurement available as a real-time analog output. The system therefore scans open-loop – at the full dynamic capability of the stage, unconstrained by servo bandwidth – while the coupling map is constructed from measured positions, not commanded voltages.

Hysteresis and creep still occur in the motion, but they no longer corrupt the data: each power sample is paired with the position at which it was actually acquired. The peak of the resulting three-dimensional power map is the true coupling maximum, and the stage can subsequently be commanded to it. The approach combines the speed advantage of open-loop scanning with the position fidelity of a sensor-based system – without requiring the servo loop to track the fast trajectory.

The 100 μm three-axis scan volume comfortably covers the capture range required after vision-based coarse positioning, while the compact 40 mm cube integrates into the confined probe-head space above a wafer chuck – alongside electrical probes, cameras and a second optical probe.

Integrated alignment engines from larger motion vendors deliver impressive turnkey algorithm performance, with fine-alignment routines completing in well under a second. For equipment builders who want a sealed subsystem, they are a legitimate choice. The PSJ approach addresses a different – and in our experience growing – customer profile: photonic test equipment manufacturers who consider the alignment strategy part of their own intellectual property and competitive differentiation. For them, PSJ supplies the precision mechanics and the analog real-time interfaces; the customer owns the algorithm, the timing, the software stack and the system integration. This division of labor avoids controller lock-in, keeps the bill of materials lean, and lets the alignment routine evolve with the customer’s test recipes instead of a vendor’s firmware roadmap.

The same fast peak-search building block – compact three-axis piezo stage, analog drive, synchronous position read-back – applies wherever light must be coupled actively between a fiber and a small aperture:

As co-packaged optics moves toward volume production in the second half of this decade, the number of optical I/Os per wafer – and therefore the number of alignments per wafer – rises steeply. Test capacity scales with alignment speed. Equipment builders who solve the alignment block early, with an architecture they control, hold a structural cost advantage.

Two TRITOR 100 SG stages with NV 40/3 CLE controllers perform the complete dual-sided fiber-to-chip peak search of an automated photonic wafer prober in approximately five seconds per test site, using externally generated 26 Hz spiral scans completed in 0.8s. The combination of open-loop scan speed and synchronous strain-gauge position read-back delivers geometrically correct coupling maps without the bandwidth penalty of closed-loop trajectory tracking. The open analog architecture leaves algorithm and system intelligence with the equipment builder – a deliberate alternative to closed, proprietary alignment engines.

If you are developing photonic test, packaging or alignment equipment and want to evaluate this architecture against your cycle-time targets, our application engineers will support you with stages, controllers, reference circuitry and measured step-response and frequency-response data for your specific drive configuration.